The present invention relates to a standard cell semiconductor integrated circuit layout definition and a method of generating a standard cell layout definition having functionally uncommitted base cells which aid subsequent design changes.
Semiconductor integrated circuits are designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to form a particular logical function. With standard cell technology, the schematic diagram or HDL specification is synthesized into standard cells of a specific cell library. Each standard cell corresponds to a logical function unit which is implemented by one or more transistors that are optimized for the cell. A series of computer-aided design tools generate a netlist of the selected cells and the interconnections between the cells. The netlist is used by a floor planner or placement tool to place the selected cells at particular locations in an integrated circuit layout pattern. The interconnections between the cells are then routed along predetermined routing layers. Once the selected cells have been placed and routed, the netlist, the cell layout definitions, the placement data and the routing data together form an integrated circuit layout definition which is used to fabricate the integrated circuit.
The integrated circuit is fabricated by depositing multiple layers on a substrate known as a wafer. The lowest, "base" layers include the active areas of the transistors, including the diffusion regions and the gate oxide areas, and the desired patterns of the polysilicon gate electrodes. These layers are fabricated through a sequence of pattern definition steps which are interspersed with other process steps such as oxidation, etching, doping and material deposition. The additive or subtractive process steps are proceeded by masking steps which define the desired geometric patterns on the wafer. One or more metal layers are then deposited on top of the base layers and-patterned to form conductive segments which interconnect the various semiconductor devices formed in the base layers. Electrical contacts or vias may be formed to electrically connect a conductive segment on one of the metal layers with a conductance segment or semiconductor device on one of the other layers on the wafer.
There is often a desire to release semiconductor designs to fabrication as early as possible in the design cycle. Subsequent design verification often results in the identification of design errors. Correction of the design errors may involve the addition of ore or more standard cells into the netlist, which results in changes or additions to the placement and routing data. Unfortunately, correction of these design errors can be extremely costly if made during the fabrication process. Correction may involve re-cutting the base layer mask set, re-cutting the metal layer mask set and, if wafer fabrication has begun, scrapping entire wafer lots.
One method of minimizing the effect of design changes on the fabrication process is to introduce extra standard cells into the initial semiconductor layout definition which can be used in the event a design change is needed. For example, extra NAND and NOR gates can be placed or "sprinkled" throughout the integrated circuit layout definition. However, this method has several disadvantages. Gate sprinkling suffers from the basic limitation that each added standard cell can perform only one specific function that is predetermined prior to the first pass of the fabrication process. Also, introducing extra cells into the initial design will have a detrimental effect on the amount of area needed to implement the design as each of the standard cells takes up space. Also, the floor planner or automatic placement tool will take these extra standard cells into account during the placement process. This reduces the quality of the placed design since the initial design will not have an optimum placement. The extra standard cells may also block valuable routing paths within one or more of the metal layers. The blocked routing paths are then unavailable to the routing tool, which effects the routability of the initial design.